PRESS RELEASE
Contact:
Megan Moran
Aldec, Inc.
(702) 990-4400 ext. 201
meganm@aldec.com
FOR IMMEDIATE RELEASE
Free E-Based FPGA Design Training
Aldec provides interactive tutorials to FPGA Designers
Henderson Nevada, October 11th, 2001-- Aldec, Inc., a leading supplier of HDL design entry and verification software for application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs), announced today that its FPGA design training is now available through the Aldec website. The presentations, which were started as part of Aldec's HDL Training Program, were developed by leading HDL analysts and are now available to users worldwide free of charge in an e-based format.
The presentations now available on the web are abridged versions of those trainings that are available in the more conventional training atmosphere through Aldec's Training Department. The decision to post trainings on the web was a move to provide tips on improving design technique and methodologies for all FPGA designers and expand customers' knowledge about the functionality of Aldec's tools. The primary objective of the trainings is to make FPGA designing as efficient as possible, and these trainings detail how to best execute elements of the design cycle while maintaining an accurate system design structure and increasing productivity.
The tutorials were structured by leading HDL analysts and trainers with extensive exposure to teaching HDL languages and tools. The presentations provide a concise medium for designers to learn about HDL applications and enable them to review those topics that will be of most benefit to their designs.
The FPGA design training details each topic and provides users with direct interaction with the Active-HDL graphical user interface (GUI), furthering the learning process. The primary advantage of the Active-HDL environment is its easy-to-use GUI and the control it provides over the entire design process.
The trainings are of benefit to all FPGA designers. There are currently seven courses that can be viewed from the website; topics include Bottom-Up Design Methodology, Top-Down Design Methodology, Design Management, Debugging, Simulation, Testbenches and Code Coverage. Other topics will be added in support of the latest trends in EDA technology and new enhancements in Active-HDL.
Availability
The FPGA design trainings will be available on Aldec's website October 11, 2001, and may be accessed at any time. As part of its continuing effort to promote the latest in technology in the EDA industry, Aldec has made these presentations available to customers free of charge and regardless of web-registration or membership.
About Aldec
Aldec, Inc. has offered PC and Workstation-based design entry and simulation solutions to FPGA and ASIC designers for more than 16 years. During this time, Aldec has signed several OEM agreements with IC vendors, such as Xilinx, Inc. (NASDAQ:XLNX) and Cypress Semiconductor Corp. (NYSE:CY). Aldec, headquartered in Henderson, Nevada, produces a universal suite of Windows, Linux and UNIX-based EDA tools that allow design engineers to implement their designs using several different design entry methods (Schematic Capture, State Machine, Block Diagram, VHDL, Verilog or ABEL). Aldec incorporates patented simulation technology and several design entry tools to provide a complete design entry and simulation solution. Founded in 1984, the company continues to evolve in the EDA market as the fastest growing verification company in the world. Additional information about Aldec is available at http://www.aldec.com.
Active-HDL is a trademark of Aldec, Inc. All other trademarks or registered
trademarks are property of their respective owners
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